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| FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver September 2008 FAN3121 / FAN3122 Single 9A High-Speed, Low-Side Gate Driver Features Industry-Standard Pin-out with Enable Input 4.5 to 18V Operating Range 11.4A Peak Sink at VDD = 12V 9.7A Sink / 7.1A Source at VOUT = 6V Inverting Configuration (FAN3121) and Non-Inverting Configuration (FAN3122) Internal Resistors Turn Driver Off If No Inputs 23ns/19ns Typical Rise/Fall Times with 10nF Load 20ns Typical Propagation Delay Time Choice of TTL or CMOS Input Thresholds MillerDriveTM Technology Available in Thermally Enhanced 3x3mm 8-Lead MLP or 8-Lead SOIC Package (Pb-Free Finish) Rated from -40C to +125C Description The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses. The drivers are available with either TTL (FAN312xT) or CMOS (FAN312xC) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. FAN312x drivers incorporate the MillerDriveTM architecture for the final output stage. This bipolar / MOSFET combination provides the highest peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process. The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industry-standard pin-out. The pin is internally pulled up to VDD for active HIGH logic and can be left open for standard operation. The FAN3121/22 is available in a 3x3mm 8-lead thermallyenhanced MLP package or an 8-lead SOIC package. Applications Synchronous Rectifier Circuits High-Efficiency MOSFET Switching Switch-Mode Power Supplies DC-to-DC Converters Motor Control VDD 1 IN EN 2 3 8 7 6 5 VDD OUT OUT GND VDD 1 IN EN 2 3 8 VDD 7 OUT 6 OUT 5 GND GND 4 GND 4 Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Ordering Information Part Number FAN3121CMPX FAN3121CMX FAN3121TMX FAN3122CMPX FAN3122CMX FAN3122TMX Non-Inverting Channels + FAN3122TMPX Enable Inverting Channels + FAN3121TMPX Enable Logic Input Threshold CMOS TTL CMOS TTL Package 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 Eco Status RoHS RoHS RoHS RoHS RoHS RoHS RoHS RoHS Packing Method Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Quantity per Reel 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package Outlines Figure 3. 3x3mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View) Thermal Characteristics(1) Package 8-Lead 3x3mm Molded Leadless Package (MLP) 8-Pin Small Outline Integrated Circuit (SOIC) JL (2) JT (3) JA (4) JB (5) JT (6) Units C/W C/W 1.2 38 64 29 42 87 2.8 41 0.7 2.3 Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 2 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver VDD 1 IN EN 2 3 8 7 6 5 VDD OUT OUT GND VDD 1 IN EN 2 3 8 VDD 7 OUT 6 OUT 5 GND GND 4 GND 4 Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated) Pin Definitions FAN3121 3 4, 5 2 FAN3122 3 4, 5 2 6, 7 Name EN GND IN OUT OUT Description Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both TTL and CMOS IN thresholds. Ground. Common ground reference for input and output circuits. Input. Gate Drive Output. Held LOW unless required input is present and VDD is above the UVLO threshold. Gate Drive Output (inverted from the input). Held LOW unless required input is present and VDD is above the UVLO threshold. Supply Voltage. Provides power to the IC. Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected to GND; NOT suitable for carrying current. 6, 7 1, 8 1, 8 VDD P1 Output Logic FAN3121 EN 0 0 1 1 (7) (7) FAN3122 OUT 0 0 1 0 EN 0 0 1 1 (7) (7) IN 0 1 1 (7) IN 0 0 (7) OUT 0 0 0 1 1 (7) 0 (7) 1 Note: 7. Default input signal if no external connection is made. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 3 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Block Diagram VDD 1 100k 8 VDD Inverting (FAN3121) UVLO VDD_OK IN 2 7 100k OUT (FAN3121) OUT (FAN3122) OUT (FAN3121) OUT (FAN3122) Non-Inverting 100k (FAN3122) VDD 100k 6 EN 3 5 GND GND 4 Figure 7. Block Diagram (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 4 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VEN VIN VOUT TL TJ TSTG ESD VDD to GND EN to GND IN to GND OUT to GND Parameter Min. -0.3 Max. 20.0 Unit V V V V C C C kV GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 +260 -55 -65 Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 2 1 +150 +150 Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VEN VIN TA Supply Voltage Range Enable Voltage EN Input Voltage IN Parameter Min. 4.5 0 0 -40 Max. 18.0 VDD VDD +125 Unit V V V C Operating Ambient Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 5 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Electrical Characteristics Unless otherwise noted, VDD=12V and TJ=-40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Supply VDD IDD VON VOFF VIL_T VIH_T IIN+ IINVHYS_T VIL_C VIH_C IIN+ IINVHYS_C VENL VENH VHYS_T RPU tD1, tD2 tD1, tD2 Output ISINK ISOURCE IPK_SINK tRISE tFALL tD1, tD2 tD1, tD2 IRVS Parameter Operating Range Supply Current, Inputs / EN Not Connected Turn-On Voltage Turn-Off Voltage (9) Conditions Min. Typ. 4.5 Max. 18.0 Unit V mA V V V TTL CMOS (8) 0.65 0.58 3.5 3.30 0.8 4.0 3.75 1.0 1.7 0.90 0.85 4.3 4.10 Inputs (FAN312xT) INx Logic Low Threshold INx Logic High Threshold Non-Inverting Input Current Inverting Input Current TTL Logic Hysteresis Voltage (9) 2.0 175 1 V A A V %VDD IN from 0 to VDD IN from 0 to VDD -1 -175 0.40 30 0.70 38 55 0.85 Inputs (FAN312xC) INx Logic Low Threshold INx Logic High Threshold Non-Inverting Input Current Inverting Input Current CMOS Logic Hysteresis Voltage Enable Logic Low Threshold Enable Logic High Threshold TTL Logic Hysteresis Voltage Enable Pull-up Resistance Propagation Delay, EN Rising (10) (10) 70 175 1 %VDD A A %VDD V V V k ns ns IN from 0 to VDD IN from 0 to VDD -1 -175 12 17 1.6 2.2 0.6 100 17 21 24 2.0 2.6 0.8 134 27 33 ENABLE (FAN3121, FAN3122) EN from 5V to 0V EN from 0V to 5V 1.2 1.8 0.2 68 8 14 OUT at VDD/2, CLOAD=1.0F, f=1kHz OUT at VDD/2, CLOAD=1.0F, f=1kHz CLOAD=1.0F, f=1kHz CLOAD=1.0F, f=1kHz CLOAD=10nF CLOAD=10nF (10) Propagation Delay, EN Falling OUT Current, Mid-Voltage, Sinking (11) 9.7 7.1 11.4 10.6 18 11 9 9 1500 23 19 18 23 29 27 28 35 A A A A ns ns ns ns mA OUT Current, Mid-Voltage, Sourcing OUT Current, Peak, Sinking Output Rise Time Output Fall Time (10) (11) (11) (11) IPK_SOURCE OUT Current, Peak, Sourcing (10) Output Propagation Delay, CMOS Inputs Output Propagation Delay, TTL Inputs Output Reverse Current Withstand (11) (10) 0 - 12VIN, 1V/ns Slew Rate 0 - 5VIN, 1V/ns Slew Rate Notes: 8. Lower supply current due to inactive TTL circuitry. 9. EN inputs have modified TTL thresholds; refer to the ENABLE section. 10. See Timing Diagrams of Figure 8 and Figure 9. 11. Not tested in production. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 6 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Timing Diagrams Figure 8. Non-Inverting Figure 9. Inverting (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 7 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 10. IDD (Static) vs. Supply Voltage (12) Figure 11. IDD (Static) vs. Supply Voltage (12) Figure 12. IDD (No-Load) vs. Frequency Figure 13. IDD (No-Load) vs. Frequency Figure 14. IDD (10nF Load) vs. Frequency (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 Figure 15. IDD (10nF Load) vs. Frequency www.fairchildsemi.com 8 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 16. IDD (Static) vs. Temperature (12) Figure 17. IDD (Static) vs. Temperature (12) Figure 18. Input Thresholds vs. Supply Voltage Figure 19. Input Thresholds vs. Supply Voltage Figure 20. Input Thresholds % vs. Supply Voltage Figure 21. Enable Thresholds vs. Supply Voltage (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 9 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 22. CMOS Input Thresholds vs. Temperature Figure 23. TTL Input Thresholds vs. Temperature Figure 24. Enable Thresholds vs. Temperature Figure 25. UVLO Thresholds vs. Temperature Figure 26. UVLO Hysteresis vs. Temperature Figure 27. Propagation Delay vs. Supply Voltage (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 10 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 28. Propagation Delay vs. Supply Voltage Figure 29. Propagation Delay vs. Supply Voltage Figure 30. Propagation Delay vs. Supply Voltage Figure 31. Propagation Delay vs. Supply Voltage Figure 32. Propagation Delays vs. Temperature Figure 33. Propagation Delays vs. Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 11 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature Figure 36. Propagation Delays vs. Temperature Figure 37. Fall Time vs. Supply Voltage Figure 38. Rise Time vs. Supply Voltage Figure 39. Rise and Fall Time vs. Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 12 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and VDD=12V unless otherwise noted. Figure 40. Rise / Fall Waveforms with 10nF Load Figure 41. Quasi-Static Source Current with VDD=12V (13) Figure 42. Quasi-Static Sink Current with VDD=12V (13) Figure 43. Quasi-Static Source Current with VDD=8V (13) V DD (2) x 4.7F ceramic 470F Al. El. FAN3121/22 IOUT 1F ceramic Current Probe LECROY AP015 IN 1kHz VOUT C LOAD 1F Figure 44. Quasi-Static Sink Current with VDD=8V (13) Figure 45. Quasi-Static IOUT / VOUT Test Circuit Notes: 12. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static IDD increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 7. 13. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current-measurement loop. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 13 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Applications Information The FAN3121 and FAN3122 family offers versions in either TTL or CMOS input configuration. In the FAN3121T and FAN3122T, the input thresholds meet industry-standard TTL-logic thresholds independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.7V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/s or faster, so the rise time from 0 to 3.3V should be 550ns or less. The FAN3121 and FAN3122 output can be enabled or disabled using the EN pin with a very rapid response time. If EN is not externally connected, an internal pullup resistor enables the driver by default. The EN pin has logic thresholds for parts with either TTL or CMOS IN thresholds. In the FAN3121C and FAN3122C, the logic input thresholds are dependent on the VDD level and, with VDD of 12V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching, even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. Figure 46. Miller DriveTM Output Architecture Under-Voltage Lockout (UVLO) The FAN312x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage lockout (UVLO) function to ensure that the IC starts in an orderly fashion. When VDD is rising, yet below the 4.0V operational level, this circuit holds the output low, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.25V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would turn the P-channel MOSFET on with VDD below 4.0V. Static Supply Current In the IDD (static) Typical Performance Characteristics, the curves are produced with all inputs / enables floating (OUT is LOW) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100k resistors on the inputs and outputs, as shown in the block diagram (see Figure 7). In these cases, the actual static IDD current is the value obtained from the curves, plus this additional current. VDD Bypassing and Layout Considerations The FAN3121 and FAN3122 are available in either 8-lead SOIC or MLP packages. In either package, the VDD pins 1 and 8 and the GND pins 4 and 5 should be connected together on the PCB. In typical FAN312x gate-driver applications, highcurrent pulses are needed to charge and discharge the gate of a power MOSFET in time intervals of 50ns or less. A bypass capacitor with low ESR and ESL should be connected directly between the VDD and GND pins to provide these large current pulses without causing unacceptable ripple on the VDD supply. To meet these requirements in a small size, a ceramic capacitor of 1F or larger is typically used, with a dielectric material such as X7R, to limit the change in capacitance over the temperature and / or voltage application ranges. www.fairchildsemi.com 14 MillerDriveTM Gate-Drive Technology FAN312x gate drivers incorporate the MillerDriveTM architecture shown in Figure 46. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the HIGH or LOW rail. The purpose of the Miller DriveTM architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Figure 47 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor CBYP and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible with the FAN312x family, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driver-MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD Turn-on threshold IN- VDD CBYP FAN3121/2 PWM VDS IN+ (VDD) OUT Figure 47. Current Path for MOSFET Turn-On Figure 48 shows the path the current takes when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. Figure 50. Inverting Startup Waveforms At power up, the FAN3122 non-inverting driver, shown in Figure 51, holds the output LOW until the VDD voltage reaches the UVLO turn-on threshold, as indicated in Figure 52. The OUT pulses magnitude follow VDD magnitude until steady-state VDD is reached. VDD IN OUT VDD CBYP FAN3121/2 VDS PWM Figure 51. Non-Inverting Driver Figure 48. Current Path for MOSFET Turn-Off VDD Turn-on threshold Operational Waveforms At power up, the FAN3121 inverting driver shown in Figure 49 holds the output LOW until the VDD voltage reaches the UVLO turn-on threshold, as indicated in Figure 50. This facilitates proper startup control of lowside N-channel MOSFETs. VDD IN OUT IN- IN+ Figure 49. Inverting Configuration The OUT pulses' magnitude follows VDD magnitude with the output polarity inverted from the input until steadystate VDD is reached. OUT Figure 52. Non-Inverting Startup Waveforms (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 15 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE = QG * VGS * fSW (2) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the "IDD (No-Load) vs. Frequency" graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC * VDD (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ = PTOTAL * JB + TB (4) In a full-bridge synchronous rectifier application, shown in Figure 53, each FAN3122 drives a parallel combination of two high-current MOSFETs, (such as FDMS8660S). The typical gate charge for each SR MOSFET is 70nC with VGS = VDD = 9V. At a switching frequency of 300kHz, the total power dissipation is: PGATE = 2 * 70nC * 9V * 300kHz = 0.378W PDYNAMIC = 2mA * 9V = 18mW PTOTAL = 0.396W (5) (6) (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB = 42C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150C; with 80% derating, TJ would be limited to 120C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120C: TB,MAX = TJ - PTOTAL * JB TB,MAX = 120C - 0.396W * 42C/W = 104C (8) (9) For comparison, replace the SOIC-8 used in the previous example with the 3x3mm MLP package with JB = 2.8C/W. The 3x3mm MLP package can operate at a PCB temperature of 118C, while maintaining the junction temperature below 120C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider tradeoffs between reducing overall circuit size with junction temperature reduction for increased reliability. where: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 16 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Typical Application Diagrams V IN V OUT B2 A2 B1 A1 BIAS FAN3122 SR EN VDD 1 IN From A1 EN 2 3 4 8 7 6 5 FAN3122 VDD OUT OUT VDD 1 IN 2 3 SR EN EN 4 8 7 6 5 From A2 VDD OUT OUT PGND AGND PGND AGND Figure 53. Full-Bridge Synchronous Rectification VIN VOUT PWM FAN3121 VBIAS VDD 1 2 3 4 P1 (AGND) 8 7 6 5 VDD OUT OUT PGND SR Enable Active HIGH IN EN AGND Figure 54. Hybrid Synchronous Rectification in a Forward Converter (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 17 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Table 1. Related Products Part Number FAN3100C FAN3100T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T FAN3121C FAN3121T FAN3122C FAN3122T Type Single 2A Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Single 9A Single 9A Single 9A Single 9A Gate Input (14) Drive Threshold (Sink/Src) +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL Logic Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channels + Enable Single Inverting Channels + Enable Single Non-Inverting Channels + Enable Single Non-Inverting Channels + Enable Package SOT23-5, MLP6 SOT23-5, MLP6 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 Note: 14. Typical currents with OUT at 6V and VDD = 12V. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 18 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Physical Dimensions 2X 0.8 MAX 2X RECOMMENDED LAND PATTERN 0.05 0.00 SEATING PLANE A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION VEEC, DATED 11/2001 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. FILENAME: MKT-MLP08Drev2 Figure 55. 3x3mm, 8-Lead Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 19 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver Physical Dimensions (Continued) 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8 0 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 56. 8-Lead SOIC Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 20 FAN3121 / FAN3122 -- Single 9A High-Speed, Low-Side Gate Driver (c) 2008 Fairchild Semiconductor Corporation FAN3121 / FAN3122 * Rev. 1.0.0 www.fairchildsemi.com 21 |
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